Pentium Pro Processor System Architecture- Tom Shanley

The primary audience for this book is hardware engineers, compiler designers, kernel folk and the like. I'm not any of those, and it's been a long, long time since I had to write any assembly language. So why did I enjoy this so much? Because the CPU is, after all, the base of everything we do, and understanding its capabilities and features is both important and interesting.

For example, did you know that the BIST (Built In Self Test) on a Pentium Pro takes some 5.5 million clock cycles? Running at 200 MHz or more, that's not even an eye blink, but imagine how exhaustive the tests must be. Did you know that the Pentium Pro actually translates IA (Intel Architecture) instructions (x86 instructions) into RISC instructions, so it really is a RISC processor that runs CISC instructions?

The Pentium Pro has lots of tricks up its sleeves. It has 40 general purpose registers, and it will use them to improve code written for previous processors. IA code generally does a lot of register shuffling. An example from the book shows this sequence:

 mov eax, 17
 add mem, eax
 mov eax, 3
 add eax, ebx
 
 

If the Pentium Pro just took those as they are, and used the registers indicated, this sequence would have to be executed serially; it could not take advantage of its ability to execute micro-ops (RISC instructions) simultaneously. But it does not use the registers that the code tells it to; it uses its "hidden" registers so that the two "mov"'s can be done at the same time, followed by the two "add"'s (also done concurrently). The Pro also has a new branch prediction algrorithm that is supposedly up to 95% successful, there is support for having one CPU follow another's work, comparing its results for every instruction the other executes, and more.

There are also fascinating little inefficiences. According to the author, at initial startup, the processor requests 8 bytes, but actually reads 32 bytes, discards 24, then does it again to get the next 8 bytes (which it already had and had thrown away!).

There's an amusing new instruction in the Pro's repertoire: it is the UD2 instruction, which is defined-pay attention!- as an undefined instruction. Obviously that's for testing; allowing the deliberate generation of an undefined opcode, but the definition of undefined does stop my brain for at least half a second.

An interesting new register, the TSC (Time Stamp Counter) counts processor clock cycles since reset (or since it was programmatically zeroed). This register was actually introduced in the Pentium, but Intel did not document it until the Pro. It's a 64 bit register; when it reaches all "ones", it wraps around to zero and starts again. No interrupt marks this momentous occurence, which is understandable once you realize how long it would take for it to reach that point. This is a 64 bit register, and the implications of 64 bit computing are fascinating. Consider that this register increments every clock cycle. Given a 200 MHz clock, that would mean it would increase its value by 200 million every second. A 32 bit register, capable of holding a maximum value of merely 4 billion or so, would overflow in about 20 seconds when forced to swallow 200 million increments each and every second. A 48 bit register would last longer: a little less than 3 years if I did the math right. But a 64 bit register, incrementing 200 million times every second, runs for thousands of years before it overflows! Doesn't that give a great picture of what 64 bit numbers really are? The author tells us that Intel promises us that the wraparound period for future processors will never be less than 10 years, which would require some unimaginable clock speeds!

The sections on bus arbitration and timing were of less interest to me. There is full coverage of the 450GX, KX and 440FX chipsets; again probably of most interest to system designers and device driver programmers.

This book also covers MMX extensions. I never realized that the MMX registers are really just the FPU registers, or if I had read that somewhere before now, it hadn't sunk in. There's a lot of little "Aha's" like that to be gleaned from this book. You will need at least a minimal background in general CPU architecture to comprehend this book, but if this review didn't leave you dumfounded, you probably have enough to both understand and enjoy it.

The Pentium Pro has been replaced by the Xeon processor. I haven't yet seen any books about that. Intel's web site does have information, of course, but that seems to be either glitzy sales overviews or bare metal engineers manuals, with little in betweeen.